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? 2000-2013 microchip technology inc. preliminary ds41140c-page 1 pic16c432 devices included in this data sheet: ? pic16c432 high performance risc cpu: ? only 35 instructions to learn ? all single cycle instructions (200 ns), except for program branches which are two-cycle ? operating speed: - dc - 20 mhz clock input - dc - 200 ns instruction cycle ? interrupt capability ? 16 special function hardware registers ? 8-level deep hardware stack ? direct, indirect and relative addressing modes peripheral features: ? 12 i/o pins with individual direction control ? high current sink/source for direct led drive ? analog comparator module with: - two analog comparators - programmable on-chip voltage reference (v ref ) module - programmable input multiplexing from device inputs and internal voltage reference - comparator outputs can be output signals ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? integrated lin transceiver ? wake-up on bus activity ? 12v battery operation for transceiver ? thermal shutdown for transceiver ? ground loss protection pin diagram special microcontroller features: ? in-circuit serial programming (icsp?) ? (via two pins) ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? brown-out reset ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power saving sleep mode ? selectable oscillator options ? four user programmable id locations cmos technology: ? low power, high speed cmos eprom/hv-cmos technology ? fully static design ? operating voltage range - 4.5v to 5.5v ? industrial and extended temperature range device program memory ram data memory pic16c432 2k x 14 128 x 8 ceramic dip, ssop, pdip 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 lin ra2/an2/v ref ra3/an3 ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 v bat v ss ra0/an0 osc1/clkin osc2/clk- out v dd rb7 rb6 pic16c432 v bat bact ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 otp 8-bit cmos mcu with lin transceiver
pic16c432 ds41140c-page 2 preliminary ? 2000-2013 microchip technology inc. table of contents 1.0 general description......................................................................................................... ............................................................. 3 2.0 pic16c432 device varieties .................................................................................................. ...................................................... 5 3.0 memory organization ......................................................................................................... .......................................................... 7 4.0 i/o ports ................................................................................................................... .................................................................. 17 5.0 lin transceiver ............................................................................................................. ............................................................. 23 6.0 timer0 module ............................................................................................................... ............................................................ 27 7.0 comparator module........................................................................................................... ......................................................... 33 8.0 voltage reference module.................................................................................................... ..................................................... 41 9.0 special features of the cpu ................................................................................................. ..................................................... 43 10.0 instruction set summary .................................................................................................... ........................................................ 59 11.0 development support........................................................................................................ ......................................................... 73 12.0 electrical specifications.................................................................................................. ............................................................ 79 13.0 dc and ac characteristics graphs and tables ................................................................................ ......................................... 91 14.0 packaging information...................................................................................................... .......................................................... 93 appendix a: code for lin communication .......................................................................................... ............................................ 97 index: ......................................................................................................................... ......................................................................... 99 on-line support................................................................................................................ ................................................................. 101 systems information and upgrade hot line ....................................................................................... ............................................... 101 reader response ................................................................................................................ .............................................................. 102 product identification system.................................................................................................. ........................................................... 103 to our valued customers it is our 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? 2000-2013 microchip technology inc. preliminary ds41140c-page 3 pic16c432 1.0 general description the pic16c432 is a 20-pin eprom-based member of the versatile pic ? family of low cost, high performance, cmos, fully-static, 8-bit microcontrollers with an inte- grated lin transceiver. the lin physical layer is implemented in hardware with a voltage range from 0v to 18v, with a 40v transient capability. the lin protocol is to be implemented in firmware, which enables flexibility with future revisions of the lin protocol. all pic ? microcontrollers employ an advanced risc architecture. the pic16c432 device has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for pro- gram branches (which require two cycles). a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16c432 microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the pic16c432 has 12 i/o pins and an 8-bit timer/ counter with an 8-bit programmable prescaler. in addi- tion, the pic16c432 adds two analog comparators with a programmable on-chip voltage reference module. the comparator module is ideally suited for applica- tions requiring a low cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). pic16c432 devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power con- sumption. there are four oscillator options, of which the single pin rc oscillator provides a low cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) mode offers power savings. the user can wake-up the chip from sleep through several external and internal interrupts and reset. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software lock- up. a uv erasable cerdip packaged version is ideal for code development, while the cost effective one-time- programmable (otp) version is suitable for production in any volume. a simplified block diagram of the pic16c432 is shown in figure 4-1. the pic16c432 series fits perfectly in automotive and industrial applications, which require lin as a commu- nication platform. the eprom technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applications with space limitations. low cost, low power, high per- formance, ease of use and i/o flexibility make the pic16c432 very versatile. 1.1 development support the pic16c432 family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer. a ?c? compiler is also available.
pic16c432 ds41140c-page 4 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 5 pic16c432 2.0 pic16c432 device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c432 product identification system section at the end of this data sheet. 2.1 uv erasable devices the uv erasable version, offered in the cerdip pack- age is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's pro mate ? programmers support pro- gramming of the pic16c432. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turn-programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code pat- terns have stabilized. the devices are identical to the otp devices, but with all eprom locations and config- uration options already programmed by the factory. certain code and prototype verification procedures apply before production shipments are available. please contact your microchip technology sales office for more details. 2.4 serialized quick-turn-programming (sqtp sm ) devices microchip offers a unique programming service where a few user defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry code, password or id number.
pic16c432 ds41140c-page 6 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 7 pic16c432 3.0 memory organization 3.1 program memory organization the pic16c432 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. only the first 2k x 14 (0000h - 07ffh) are implemented for the pic16c432. accessing a location above these boundaries will cause a wrap-around within the first 2k x 14 space. the reset vector is at 0000h and the interrupt vector is at 0004h (figure 3-1). figure 3-1: program memory map and stack for the pic16c432 3.2 data memory organization the data memory (figure 3-2) is partitioned into two banks, which contain the general purpose registers and the special function registers. bank 0 is selected when the rp0 bit is cleared. bank 1 is selected when the rp0 bit (status <5>) is set. the special function registers are located in the first 32 locations of each bank. register locations 20-7fh (bank 0) and a0-bfh (bank 1) are general purpose registers implemented as static ram. some special purpose registers are mapped in bank 1. in the microcontroller, address space f0h-ffh (bank 1) is mapped to 70-7fh (bank 0) as common ram. 3.2.1 general purpose register file the register file is organized as 128 x 8 in the pic16c432. each is accessed either directly or indi- rectly through the file select register fsr (section 3.4). pc<12:0> 13 000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2
pic16c432 ds41140c-page 8 preliminary ? 2000-2013 microchip technology inc. figure 3-2: data memory map for the pic16c432 3.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (table 3-1). these registers are static ram. the special registers can be classified into two sets (core and peripheral). the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations,read as '0'. note 1: not a physical register. file address general purpose register accesses 70h-7fh f0h linintf
? 2000-2013 microchip technology inc. preliminary ds41140c-page 9 pic16c432 table 3-1: special registers for the pic16c432 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 16 01h tmr0 timer0 module?s register xxxx xxxx 27 02h pcl program counter's (pc) least significant byte 0000 0000 15 03h status irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 10 04h fsr indirect data memory address pointer xxxx xxxx 16 05h porta ? ? ? ra4 ra3 ra2 linrx ra0 ---x 0000 17 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 20 07h ? unimplemented ? ? 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 15 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 12 0ch pir1 ?cmif ? ? ? ? ? ? -0-- ---- 13 0dh-1eh ? unimplemented ? ? 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 33 bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 16 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 11 82h pcl program counter's (pc) least significant byte 0000 0000 15 83h status irp rp1 rp0 to pd zdcc 0001 1xxx 10 84h fsr indirect data memory address pointer xxxx xxxx 16 85h trisa ? ? ? trisa4 trisa3 trisa2 tlinrx (3) trisa0 ---1 1111 17 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 20 87h ? unimplemented ? ? 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 15 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 12 8ch pie1 ?cmie ? ? ? ? ? ? -0-- ---- 13 8dh ? unimplemented ? ? 8eh pcon ? ? ? ? ? ?por bod ---- --0x 14 8fh-9eh ? unimplemented ? ? 90h linintf ? ? ? ? ?lintx ?linv dd ---- -1-1 23 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 41 legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: other (non power-up) resets include mclr reset, brown-out reset and watchdog timer reset during normal operation. 2: irp & rpi bits are reserved; always maintain these bits clear. 3: tlinrx must set to ?1? at all times.
pic16c432 ds41140c-page 10 preliminary ? 2000-2013 microchip technology inc. 3.2.2.1 status register the status register, shown in register 3-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000uu1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bit. for other instructions, not affecting any status bits, see the ?instruction set summary?. register 3-1: status register (address 03h or 83h) note 1: the irp and rp1 bits (status<7:6>) are not used by the pic16c432 and should be programmed as ?0'. use of these bits as general purpose r/w bits is not recommended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit7 bit0 bit 7 irp: ? the irp bit is reserved on the pic16c432, always maintain this bit clear bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) ? 11 = bank 3 (180h - 1ffh) ? 10 = bank 2 (100h - 17fh) ? 01 = bank 1 (80h - ffh) ? 00 = bank 0 (00h - 7fh) ? each bank is 128 bytes. the rp1 bit is reserved, always maintain this bit clear. bit 4 to : timeout bit ? 1 = after power-up, clrwdt instruction, or sleep instruction ? 0 = a wdt timeout occurred bit 3 pd : power-down bit ? 1 = after power-up or by the clrwdt instruction ? 0 = by execution of the sleep instruction bit 2 z : zero bit ? 1 = the result of an arithmetic or logic operation is zero ? 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (for borrow the polarity is reversed) ? 1 = a carry-out from the 4th low order bit of the result occurred ? 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf, addlw, sublw, subwf instructions) ? 1 = a carry-out from the most significant bit of the result occurred ? 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2000-2013 microchip technology inc. preliminary ds41140c-page 11 pic16c432 3.2.2.2 option register the option register is a readable and writable register which contains various control bits to configure the tmr0/wdt prescaler, the external rb0/int interrupt, tmr0 and the weak pull-ups on portb. register 3-2: option register (address 81h) note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt (psa = 1). r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit7 bit0 bit 7 rbpu : portb pull-up enable bit ? 1 = portb pull-ups are disabled ? 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit ? 1 = interrupt on rising edge of rb0/int pin ? 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit ? 1 = transition on ra4/t0cki pin ? 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit ? 1 = increment on high-to-low transition on ra4/t0cki pin ? 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit ? 1 = prescaler is assigned to the wdt ? 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0> : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c432 ds41140c-page 12 preliminary ? 2000-2013 microchip technology inc. 3.2.2.3 intcon register the intcon register is a readable and writable register which contains the various enable and flag bits for all interrupt sources, except the comparator module. see section 3.2.2.4 and section 3.2.2.5 for a description of the comparator enable and flag bits. register 3-3: intcon register (address 0bh or 8bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif bit7 bit0 bit 7 gie: global interrupt enable bit ? 1 = enables all unmasked interrupts ? 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit ? 1 = enables all un-masked peripheral interrupts ? 0 = disables all peripheral interrupts bit 5 t0ie : tmr0 overflow interrupt enable bit ? 1 = enables the tmr0 interrupt ? 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit ? 1 = enables the rb0/int external interrupt ? 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit ? 1 = enables the rb port change interrupt ? 0 = disables the rb port change interrupt bit 2 t0if : tmr0 overflow interrupt flag bit ? 1 = tmr0 register has overflowed (must be cleared in software) ? 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit ? 1 = the rb0/int external interrupt occurred (must be cleared in software) ? 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit ? 1 = when at least one of the rb<7:4> pins changed state (must be cleared in software) ? 0 = none of the rb<7:4> pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2000-2013 microchip technology inc. preliminary ds41140c-page 13 pic16c432 3.2.2.4 pie1 register this register contains the individual enable bit for the comparator interrupt. register 3-4: pie1 register (address 8ch) 3.2.2.5 pir1 register this register contains the individual flag bit for the com- parator interrupt. register 3-5: pir1 register (address 0ch) u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ?cmie ? ? ? ? ? ? bit7 bit0 bit 7 unimplemented: read as '0' bit 6 cmie : comparator interrupt flag bit ? 1 = enables the comparator interrupt ? 0 = disables the comparator interrupt bit 5-0 unimplemented: read as '0' legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ?cmif ? ? ? ? ? ? bit7 bit0 bit 7 unimplemented: read as '0' bit 6 cmif : comparator interrupt flag bit ? 1 = comparator input has changed ? 0 = comparator input has not changed bit 5-0 unimplemented: read as '0' legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c432 ds41140c-page 14 preliminary ? 2000-2013 microchip technology inc. 3.2.2.6 pcon register the pcon register contains flag bits to differentiate between a power-on reset, an external mclr reset, wdt reset or a brown-out reset. register 3-6: pcon register (address 8eh)) note: bod is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bod is cleared, indicating a brown-out has occurred. the bod status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?por bod bit7 bit0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit ? 1 = no power-on reset occurred ? 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bod : brown-out reset status bit ? 1 = no brown-out reset occurred ? 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2000-2013 microchip technology inc. preliminary ds41140c-page 15 pic16c432 3.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-3 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower exam- ple in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 3-3: loading of pc in different situations 3.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note, ?implementing a table read? (an556). 3.3.2 stack the pic16c432 family has an 8 level deep x 13-bit wide hardware stack (figure 3-1 and figure 3-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a ret- fie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instruction/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address.
pic16c432 ds41140c-page 16 preliminary ? 2000-2013 microchip technology inc. 3.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no- operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 3-4. however, irp is not used in the pic16c432. a simple program to clear ram location 20h-2fh using indirect addressing is shown in example 3-1. example 3-1: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next ;yes continue continue: figure 3-4: direct/indirect addressing pic16c432 for memory map detail see figure 3-2 and figure 3-2. note 1: the rp1 and irp bits are reserved; always maintain these bits clear. data memory indirect addressing direct addressing bank select location select rp1 rp0 (1) 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used
? 2000-2013 microchip technology inc. preliminary ds41140c-page 17 pic16c432 4.0 i/o ports the pic16c432 parts have two ports, porta and portb. some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 4.1 porta and trisa registers porta is a 5-bit wide latch. ra4 is a schmitt trigger input and an open drain output. port ra4 is multiplexed with the t0cki clock input. all other ra port pins have schmitt trigger input levels and full cmos output driv- ers. all pins have data direction bits (tris registers), which can configure these pins as input or output. a '1' in the trisa register puts the corresponding out- put driver in a hi-impedance mode. a '0' in the trisa register puts the contents of the output latch on the selected pin(s). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. the porta pins are multiplexed with comparator and voltage reference functions. the operation of these pins are selected by control bits in the cmcon (comparator control register) register and the vrcon (voltage reference control register) register. when selected as a comparator input, these pins will read as '0's. figure 4-1: block diagram of ra0 pins trisa controls the direction of the ra pins, even when they are being used as comparator inputs. the user must make sure to keep the pins configured as inputs when using them as comparator inputs. the ra2 pin will also function as the output for the volt- age reference. when in this mode, the v ref pin is a very high impedance output. the user must configure trisa<2> bit as an input and use high impedance loads. in one of the comparator modes defined by the cmcon register, pins ra3 and ra4 become outputs of the comparators. the trisa<4:3> bits must be cleared to enable outputs to use this function. example 4-1: initializing porta data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog vss v dd i/o pin q d q ck input mode d q en to comparator schmitt trigger input buffer v dd note: on reset, the trisa register is set to all inputs. the digital inputs are disabled and the comparator inputs are forced to ground, to reduce excess current con- sumption. clrf porta ;initialize porta by setting ;output data latches movlw 0x07 ;turn comparators off and movwf cmcon ;enable pins for i/o ;functions bsf status, rp0 ;select bank1 movlw 0x1f ;value used to initialize ;data direction movwf trisa ;set ra<4:0> as inputs ;trisa<7:5> are always ;read as '0'. note 1: bact pin is an output and must be left open if unused.
pic16c432 ds41140c-page 18 preliminary ? 2000-2013 microchip technology inc. figure 4-2: block diagram of ra2 pin figure 4-3: block di agram of ra3 pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog vss v dd ra2 pin q d q ck input mode d q en to comparator schmitt trigger input buffer v roe v ref v dd data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog vss v dd ra3 pin q d q ck d q en to comparator schmitt trigger input buffer input mode comparator output comparator mode = 110 v dd
? 2000-2013 microchip technology inc. preliminary ds41140c-page 19 pic16c432 figure 4-4: block di agram of ra4 pin table 4-1: porta functions table 4-2: summary of regist ers associated with porta name bit # buffer type function ra0/an0 bit0 st input/output or comparator input. linrx bit1 st lin receive pin. ra2/an2/v ref bit2 st input/output or comparator input or v ref output. ra3/an3 bit3 st input/output or comparator input/output. ra4/t0cki bit4 st input/output or external clock input for tmr0 or comparator output. ? output is open drain type. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por value on all other resets 05h porta ? ? ? ra4 ra3 ra2 linrx ra0 ---x 0000 ---u 0000 85h trisa ? ? ? trisa4 trisa3 trisa2 tlinrx (2) trisa0 ---1 1111 ---1 1111 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: ? = unimplemented locations, read as ?0?, x = unknown, u = unchanged note 1: shaded bits are not used by porta. 2: tlinrx must be set to ?1? at all times. data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta vss ra4 pin q d q ck d q en tmr0 clock input schmitt trigger input buffer comparator output comparator mode = 110
pic16c432 ds41140c-page 20 preliminary ? 2000-2013 microchip technology inc. 4.2 portb and trisb registers portb is an 8-bit wide, bi-directional port. the corresponding data direction register is trisb. a '1' in the trisb register puts the corresponding output driver in a high impedance mode. a '0' in the trisb register puts the contents of the output latch on the selected pin(s). reading portb register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. each of the portb pins has a weak internal pull-up ( ? 200 ? a typical). a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (option<7>) bit. the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on power-on reset. four of portb?s pins, rb<7:4>, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb<7:4> pin con- figured as an output is excluded from the interrupt-on- change comparison). the input pins of rb<7:4> are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb<7:4> are or?ed together to generate the rbif interrupt (flag latched in intcon<0>). figure 4-5: blo ck diagram of rb<7:4> pins this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. this interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow easy interface to a key pad and make it possible for wake-up on key depression. (see an552, ?implement- ing wake-up on key strokes?.) the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. figure 4-6: block diagram of rb<3:0> pins data latch from other rbpu (1) p v dd i/o pin q d ck q d ck qd en qd en data bus wr portb wr trisb (1) set rbif tris latch rd trisb rd portb rb<7:4> pins weak pull-up rd port latch ttl input buffer st buffer rb<7:6> in serial programming mode note 1: trisb = 1 enables weak pull-up if rbpu = 0 (option<7>). note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may not get set. data latch rbpu (1) p v dd q d ck q d ck qd en data bus wr portb wr trisb (1) rd trisb rd portb weak pull-up rd port rb0/int ttl input buffer st buffer i/o pin tris latch note 1: trisb = 1 enables weak pull-up if rbpu = 0 (option<7>).
? 2000-2013 microchip technology inc. preliminary ds41140c-page 21 pic16c432 table 4-3: portb functions table 4-4: summary of regist ers associated with portb name bit # buffer type function rb0/int bit0 ttl/st (1) input/output or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock pin. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data pin. legend: st = schmitt trigger, ttl = ttl input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: u = unchanged, x = unknown note 1: shaded bits are not used by portb.
pic16c432 ds41140c-page 22 preliminary ? 2000-2013 microchip technology inc. 4.3 i/o programming considerations 4.3.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs defined. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and re-written to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (i.e., bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 4-2 shows the effect of two sequential read- modify-write instructions (i.e., bcf, bsf , etc.) on an i/o port. a pin actively outputting a low or high should not be driven from external devices at the same time, in order to change the level on this pin (?wired-or?, ?wired-and?). the resulting high output currents may damage the chip. example 4-2: read-modify-write instructions on an ? i/o port 4.3.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 4- 7). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin volt- age to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu, rather than the new state. when in doubt, it is better to separate these instructions with a nop, or another instruction not accessing this i/o port. figure 4-7: successive i/o operation ; initial port settings: portb<7:4> inputs portb<3:0> outputs ; portb<7:6> have external pull-up and are not connected ; to other circuitry ; ; port latch port pins ; ------------------ ---------------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ; note: that the user may have expected the pin values to ; be 00pp pppp . the 2nd bcf caused rb7 to be latched as ; the pin value (high). note: this example shows write to portb followed by a read from portb. note that: ? data setup time = (0.25 t cy - t pd ) where t cy = instruction cycle and t pd = propagation delay of q1 cycle to output valid. therefore, at higher clock frequencies, a write followed by a read may be problematic. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 rb <7:0> port pin sampled here pc pc + 1 pc + 2 pc + 3 nop nop movf portb, w read portb movwf portb write to portb pc instruction fetched t pd execute movwf portb execute movf portb, w execute nop rb<7:0> pc instruction fetched movwf portb movf portb, w nop nop execute movwf portb execute movf portb, w execute nop
? 2000-2013 microchip technology inc. preliminary ds41140c-page 23 pic16c432 5.0 lin transceiver the pic16c432 has an integrated lin transceiver which allows the microcontroller to communicate via lin. the lin protocol is handled by the microcontroller. the conversion from 5v signal to lin signals is han- dled by the transceiver. 5.1 the lin protocol the lin protocol is not described within this document. for further information regarding the lin protocol, please refer to www.lin-subbus.org. 5.2 lin interfacing the lin protocol is implemented and programmed by the user, using the lintx and linrx bits, which are used to interface to the transceiver. the lin firmware transmits by toggling the lintx bit in the linintf reg- ister and is read by reading the linrx bit in the porta register. all aspects of the protocol are handled by soft- ware (i.e., bit-banged), where the transceiver is used as the physical interface to the lin network. for lin software implementation, please refer to micro- chip's website (www.microchip.com). if the lintx bit is left cleared, no other nodes on the network will be able to communicate on the lin for this is the dominate state for the protocol. the transceiver can be powered down by clearing the linvdd bit in the linintf register. this can be useful to reduce current consumption but does not allow the microcontroller to wake-up on lin activity because the transceiver will be disabled. it is recommended that the firmware verify each bit transmitted, by comparing the lintx and linrx bits, to ensure no bus contention or hardware failure has occurred. the lintx bit has no associated tris bit and is always an output. the linrx bit has an associated tris bit, tlinrx, in the trisa register. 5.3 lin hardware interface figure 6-1 shows how to implement a hardware lin interface in a master configuration and figure 6-2 in a slave configuration using the pic16c432. figure 6-3 shows how to implement the hardware for a master configuration using bact pin to generate a wake-up interrupt using rb0. the transceiver has an internal series resistor and diode, as defined in the lin 1.2 specification, connecting v bat and lin. 5.4 thermal shutdown in thermal shutdown, the lin output is disabled instan- taneously. the output transistor is turned off, regard- less of the input level at pin lintx bit and only a limited current can flow into the receiver connected to the lin pin. 5.5 wake-up from sleep upon bus activity the pic16c432 can wake-up from sleep upon bus activity in two ways: 1. with the use of the comparators. 2. connecting bact to one of portb<0,4:7> pins. in case the comparators are used to wake-up the device upon bus activity, a reference to the lin signal has to be supplied. this is usually v dd /2. the refer- ence can either be an external reference or the internal voltage reference. once the device is in sleep mode, the comparator interrupt will wake-up the device. on reset, linrx is configured as an analog comparator input (section 8.1 of data sheet) which can be used to generate an interrupt to wake-up the device from sleep on bus activity. the linrx bit will not receive data from the bus configured as an analog input, there- fore, after wake-up from comparator interrupt or reset, linrx must be configured as a digital input to read the bus. the bact output is a cmos-levels representation of the lin pin. this signal can be routed to one of the portb<0,4:7> pins. the rb0/int external interrupt or portb<4:7> interrupt-on-change wakes up the device from sleep. any one of the five portb pins can be used for wake-up where portb<0> offers multiple configuration options (section 10.5.1 of data sheet) and portb<4:7> are interrupt-on-change (section 10.5.3 of data sheet). note: the lintx is bit 2 of the linintf register. note: tlinrx, bit 1 of trisa register, must be set to '1' at all times. note: no resistor is required between v bat pin and 12v supply and for slave configura- tion, no resistor is required between v bat and lin. note: bact pin is an output and must be left open if unused.
pic16c432 ds41140c-page 24 preliminary ? 2000-2013 microchip technology inc. figure 5-1: typical lin bus master application figure 5-2: typical lin bus slave application to l i n b u s v dd v ss v bat lin +5v pic16c432 1k ? bact +12v note 1: refer to lin bus specification. 2: bact pin should be left open if not used. note 2 note 1 to l i n b u s v dd v ss v bat lin +5v pic16c432 bact +12v note 1: may not be required. 2: bact pin should be left open if not used. note 2 note 1
? 2000-2013 microchip technology inc. preliminary ds41140c-page 25 pic16c432 figure 5-3: lin bus application using wake-up interrupt to l i n b u s v dd v ss v bat lin +5v pic16c432 1k ? bact rb0 +12v note 1 note 1: may not be required. 2: for master configuration only. note 2
pic16c432 ds41140c-page 26 preliminary ? 2000-2013 microchip technology inc. register 5-1: linintf register (address: 90h) table 5-1: summary of registers asso ciated with lin transceiver u-0 u-0 u-0 u-0 u-0 r/w-1 u-0 r/w-1 ? ? ? ? ?lintx ?linvdd bit 7 bit 0 bit 7-3 unimplemented: read as '0' bit 2 lintx : lin bus transmit bit 1 = lin bus line is high 0 = lin bus line is low bit 1 unimplemented : read as '0' bit 0 linvdd: lin bus transceiver v dd supply bit 1 = v dd is supplied to the lin bus transceiver via microcontroller 0 = v dd is not supplied to the lin bus transceiver note 1: transceiver v dd is same as microcontroller v dd . legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 05h porta ? ? ? ra4 ra3 ra2 linrx ra0 ---x 0000 ---u 0000 85h trisa ? ? ? trisa4 trisa3 trisa2 tlinrx (2) trisa0 ---1 1111 ---1 1111 90h linintf ? ? ? ? ?lintx ?linv dd ---- -1-1 ---- -1-1 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ?0?. note 1: shaded bits are not used by lin transceiver 2: tlinrx must be set to ?1? at all times.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 27 pic16c432 6.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the tmr0 will increment every instruction cycle (without prescaler). if timer0 is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to tmr0. counter mode is selected by setting the t0cs bit. in this mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the source edge (t0se) control bit (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.2. the prescaler is shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.3 details the operation of the prescaler. 6.1 timer0 interrupt timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflow sets the t0if bit. the interrupt can be masked by clearing the t0ie bit (intcon<5>). the t0if bit (intcon<2>) must be cleared in software by the timer0 module interrupt service routine, before re- enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep, since the timer is shut-off during sleep. see figure 6-4 for timer0 inter- rupt timing. figure 6-1: timer0 block diagram figure 6-2: timer0 (tmr 0) timing: internal cl ock/no prescaler note 1: bits t0se, t0cs, ps2, ps1, ps0 and psa are located in the option register. 2: the prescaler is shared with th e watchdog timer (figure 6-6). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 ps out (2 t cy delay) ps out data bus 8 set flag bit t0if on overflow psa ps<2:0> pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed
pic16c432 ds41140c-page 28 preliminary ? 2000-2013 microchip technology inc. figure 6-3: timer0 timing: internal clock/prescale 1:2 figure 6-4: timer0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) tmr0 timer t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction flow pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h interrupt latency time note 1: t0if interrupt flag is sampled here (every q1). 2: interrupt latency = 3tcy, where tcy = instruction cycle time. 3: clkout is available only in rc oscillator mode.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 29 pic16c432 6.2 using timer0 with external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns), divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.2.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the tmr0 is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling (3) (1) note 1: delay from clock input change to timer0 increment is 3t osc to 7t osc (duration of q = t osc ). there- fore, the error in measuring the interval between two edges on timer0 input = 4 t osc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs.
pic16c432 ds41140c-page 30 preliminary ? 2000-2013 microchip technology inc. 6.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 6-6). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. note that there is only one prescaler available, which is mutually exclusive between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (i.e., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. figure 6-6: block diag ram of the timer0/wdt prescaler t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1mux m u x m u x watchdog timer psa 0 1 0 1 wdt timeout ps<2:0> 8 psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs note 1: t0se, t0cs, psa, ps<2:0> are bits in the option register.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 31 pic16c432 6.3.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to wdt. example 6-1: changing prescaler (timer0 ? wdt) 1.bcf status, rp0 ;skip if already in ? ; bank 0 2.clrwdt ;clear wdt 3.clrf tmr0 ;clear tmr0 & prescaler 4.bsf status, rp0 ;bank 1 5.movlw '00101111?b ;these 3 lines (5, 6, 7) ? 6.movwf option ; are required only ? ; if desired ps<2:0> ? ; are 7.clrwdt ; 000 or 001 8.movlw '00101xxx?b ;set postscaler to 9.movwf option ; desired wdt rate 10.bcf status, rp0 ;return to bank 0 to change prescaler from the wdt to the tmr0 module, use the sequence shown in example 6-2. this precaution must be taken, even if the wdt is disabled. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ? ;prescaler bsf status, rp0 movlw b'xxxx0xxx' ;select tmr0, new ? ;prescale value and ? ;clock source movwf option_reg bcf status, rp0 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por value on all other resets 01h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa ? ? ?trisa4 trisa3 trisa2 tlinrx (2) trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented locations, read as ?0?, x = unknown, u = unchanged note 1: shaded bits are not used by tmr0 module. 2: tlinrx must be set to ?1? at all times.
pic16c432 ds41140c-page 32 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 33 pic16c432 7.0 comparator module the comparator module contains two analog comparators. the inputs to the comparators are multiplexed with the ra0 through ra3 pins. the on- chip voltage reference (section 8.0) can also be an input to the comparators. the cmcon register, shown in register 7-1, controls the comparator input and output multiplexers. a block diagram of the comparator is shown in figure 7-1. register 7-1: cmcon register (address 1fh) 7.1 comparator configuration there are eight modes of operation for the comparators. the cmcon register is used to select the mode. figure 7-1 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in table 12-1. r-0 r-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out ? ?ciscm2cm1cm0 bit7 bit0 bit 7 c2out : comparator 2 output bit 1 = c2 v in + > c2 v in - ? 0 = c2 v in + < c2 v in - bit 6 c1out : comparator 1 output bit 1 = c1 v in + > c1 v in - ? 0 = c1 v in + < c1 v in - bit 5-4 unimplemented: read as '0' bit 3 cis : comparator input switch bit when cm<2:0> = 001 : ? 1 = c1 v in - connects to ra3 ? 0 = c1 v in - connects to ra0 when cm<2:0> = 010 : ? 1 = c1 v in - connects to ra3 ? c2 v in - connects to ra2 ? 0 = c1 v in - connects to ra0 ? c2 v in - connects to linrx bit 2-0 cm<2:0> : comparator mode bits ? (see figure 7-1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: comparator interrupts should be disabled during a comparator mode change, other- wise a false interrupt may occur.
pic16c432 ds41140c-page 34 preliminary ? 2000-2013 microchip technology inc. figure 7-1: comparator i/o operating modes - + c1 - + c2 ra0/an0 off (read as ?0?) off (read as ?0?) ra3/an3 linrx ra2/an2 a a a a comparators reset cm<2:0> = 000 v in - v in + v in - v in + - + c1 - + c2 ra0/an0 off (read as ?0?) off (read as ?0?) ra3/an3 linrx ra2/an2 d d d d comparators off cm<2:0> = 111 v in - v in + v in - v in + - + c1 - + c2 ra0/an0 ra3/an3 linrx ra2/an2 a a a a two common reference comparators cm<2:0> = 011 v in - v in + v in - v in + c1out c2out - + c1 - + c2 ra0/an0 ra3/an3 linrx ra2/an2 a d a a two common reference comparators cm<2:0> = 011 v in - v in + v in - v in + c1out c2out - + c1 - + c2 ra0/an0 ra3/an3 linrx ra2/an2 d d a a one independent comparators cm<2:0> = 101 v in - v in + v in - v in + c2out off (read as ?0?) - + c1 - + c2 ra0/an0 ra3/an3 linrx ra2/an2 cis=0 four inputs multiplexed to cm<2:0> = 010 v in + v in - v in + c1out c2out v in - cis=1 a a cis=0 cis=1 a a from v ref module two comparators - + c1 - + c2 ra0/an0 off (read as ?0?) off (read as ?0?) ra3/an3 linrx ra2/an2 a d a a two common reference comparators with outputs cm<2:0> = 110 v in - v in + v in - v in + open drain ra4 - + c1 - + c2 ra0/an0 ra3/an3 linrx ra2/an2 cis=0 three inputs multiplexed to cm<2:0> = 001 v in + v in - v in + c1out c2out v in - cis=1 a a a two comparators a legend: a = analog input, port reads ?0? always d = digital input cis = cmcon<3>, comparator input switch
? 2000-2013 microchip technology inc. preliminary ds41140c-page 35 pic16c432 the code example in example 7-1 depicts the steps required to configure the comparator module. ra3 and ra4 are configured as digital output. ra0 and ra1 are configured as the v- inputs and ra2 as the v+ input to both comparators. example 7-1: initializing comparator module 7.2 comparator operation a single comparator is shown in figure 7-2 , along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 7-2 represent the uncertainty due to input offsets and response time. 7.3 comparator reference an external or internal reference signal may be used, depending on the comparator operating mode. the analog signal that is present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 7-2). flag_reg equ 0x20 clrf flag_reg ;init flag register clrf porta ;init porta movf cmcon,w ;move comparator contents to w andlw 0xc0 ;mask comparator bits iorwf flag_reg,f ;store bits in flag register movlw 0x03 ;init comparator mode movwf cmcon ;cm<2:0> = 011 bsf status,rp0 ;select bank1 movlw 0x07 ;initialize data direction movwf trisa ;set ra<2:0> as inputs ;ra<4:3> as outputs ;trisa<7:5> always read ?0? bcf status,rp0 ;select bank 0 call delay 10 ;10ms delay movf cmcon,f ;read cmcon to end change condition bcf pir1,cmif ;clear pending interrupts bsf status,rp0 ;select bank 1 bsf pie1,cmie ;enable comparator interrupts bcf status,rp0 ;select bank 0 bsf intcon,peie ;enable peripheral interrupts bsf intcon,gie ;global interrupt enable
pic16c432 ds41140c-page 36 preliminary ? 2000-2013 microchip technology inc. figure 7-2: single comparator 7.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 7.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 8.0, voltage reference module, contains a detailed description of the voltage refer- ence module that provides this signal. the internal ref- erence signal is used when the comparators are in mode cm<2:0> = 010 (figure 7-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 7.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs, otherwise the maximum delay of the comparators should be used (table 12.1 ). + - v in + v in - output output v in - v in +
? 2000-2013 microchip technology inc. preliminary ds41140c-page 37 pic16c432 7.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read only. the comparator outputs may also be directly output to the ra3 and ra4 i/o pins. when the cm<2:0> = 110 , multiplexors in the output path of the ra3 and ra4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 7- 3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra3 and ra4 pins while in this mode. note 1: when reading the port register, all pins configured as analog inputs will read as a ?0?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is speci- fied.
pic16c432 ds41140c-page 38 preliminary ? 2000-2013 microchip technology inc. figure 7-3: comparator output block diagram d q en to ra3 or ra4 pin data bus rd cmcon set multiplex cmif bit - + q cl port pins rd cmcon nreset from other comparator en d
? 2000-2013 microchip technology inc. preliminary ds41140c-page 39 pic16c432 7.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that has occurred. the cmif bit, pir1<6>, is the comparator interrupt flag. the cmif bit must be reset by clearing ?0?. since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. the cmie bit (pie1<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon. this will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. 7.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each comparator that is operational will consume additional current as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 7.8 effects of a reset a device reset forces the cmcon register to its reset state. this forces the comparator module to be in the comparator reset mode, cm<2:0> = 000 . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered down during the reset interval. 7.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 7-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latchup may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir1<6>) interrupt flag may not get set.
pic16c432 ds41140c-page 40 preliminary ? 2000-2013 microchip technology inc. figure 7-4: analog input model table 7-1: registers associated with comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por value on all other resets 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 ?cmif ? ? ? ? ? ? -0-- ---- -0-- ---- 8ch pie1 ?cmie ? ? ? ? ? ? -0-- ---- -0-- ---- 85h trisa ? ? ? trisa4 trisa3 trisa2 tlinrx (1) trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented, read as ?0?, x = unknown, u = unchanged note 1: tlinrx must be set to ?1? at all times. va r s < 10 k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend c pin = input capacitance ? v t = threshold voltage ? i leakage = leakage current at the pin due to various junctions ? r ic = interconnect resistance ? r s = source impedance ? va = analog voltage
? 2000-2013 microchip technology inc. preliminary ds41140c-page 41 pic16c432 8.0 voltage reference module the voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. the resistor ladder is segmented to provide two ranges of v ref values and has a power-down function to conserve power when the reference is not being used. the vrcon register controls the operation of the reference as shown in register 8-1. the block diagram is given in figure 8-1. 8.1 configuring the voltage reference the voltage reference can output 16 distinct voltage levels for each range. the equations used to calculate the output of the voltage reference are as follows: if v rr = 1: v ref = (v r <3:0>/24) x v dd if v rr = 0: v ref = (v dd x 1/4) + (v r <3:0>/32) x v dd the setting time of the voltage reference must be considered when changing the v ref output (table 12.1). example 8-1 shows an example of how to configure the voltage reference for an output volt- age of 1.25v with v dd = 5.0v. register 8-1: vrcon register (address 9fh) figure 8-1: voltage reference block diagram r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 v ren v roe v rr ?v r3 v r2 v r1 v r0 bit7 bit0 bit 7 v ren : v ref enable bit ? 1 = v ref circuit powered on ? 0 = v ref circuit powered down, no i dd drain bit 6 v roe : v ref output enable bit ? 1 = v ref is output on ra2 pin ? 0 = v ref is disconnected from ra2 pin bit 5 v rr : v ref range selection bit ? 1 = low range ? 0 = high range bit 4 unimplemented: read as '0' bit 3-0 v r <3:0>: v ref value selection 0 ? v r [3:0] ? 15 ? when v rr = 1: v ref = (v r <3:0>/ 24) * v dd ? when v rr = 0: v ref = 1/4 * v dd + (v r <3:0>/ 32) * v dd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note 1: r is defined in table 12-2 . v rr 8r v r 3 v r 0 (from vrcon<3:0>) 16-1 analog mux 8r r r r r v ren v ref 16 stages
pic16c432 ds41140c-page 42 preliminary ? 2000-2013 microchip technology inc. example 8-1: voltage reference configuration 8.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 8- 1) keep v ref from approaching v ss or v dd . the volt- age reference is v dd derived and therefore, the v ref output changes with fluctuations in v dd . the absolute accuracy of the voltage reference can be found in table 12-2. 8.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer timeout, the contents of the vrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 8.4 effects of a reset a device reset disables the voltage reference by clearing bit v ren (vrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit v roe (vrcon<6>) and selects the high voltage range by clearing bit v rr (vrcon<5>). the v ref value select bits, vrcon<3:0>, are also cleared. 8.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the ra2 pin if the trisa<2> bit is set and the v roe bit, vrcon<6>, is set. enabling the voltage reference output onto the ra2 pin, with an input signal present, will increase current consumption. connecting ra2 as a digital output with v ref enabled will also increase current consumption. the ra2 pin can be used as a simple d/a output with limited drive capability. due to the limited drive capability, a buffer must be used in conjunction with the voltage reference output for external connections to v ref . figure 8-2 shows an example buffering technique. figure 8-2: voltage refere nce output buffer example table 8-2: registers associated with voltage reference movlw 0x02 ; 4 inputs muxed movwf cmcon ; to 2 comps. bsf status,rp0 ; go to bank 1 movlw 0x07 ; ra3-ra0 are movwf trisa ; outputs movlw 0xa6 ; enable v ref movwf vrcon ; low range ; set v r <3:0>=6 bcf status,rp0 ; go to bank 0 call delay10 ; 10 ? s delay address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por/bod value on all other resets 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 85h trisa ? ? ? trisa4 trisa3 trisa2 tlinrx (1) trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented, read as ?0? note 1: tlinrx must be set to ?1? at all times. v ref output + ? ? ? v ref module voltage reference output impedance r (1) ra2 note 1: r is dependent upon the voltage reference conf iguration vrcon<3:0> and vrcon<5>.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 43 pic16c432 9.0 special features of the cpu special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. the pic16c432 device has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: 1. osc selection 2. reset ? power-on reset (por) ? power-up timer (pwrt) ? oscillator start-up timer (ost) ? brown-out reset (bod) 3. interrupts 4. watchdog timer (wdt) 5. sleep 6. code protection 7. id locations 8. in-circuit serial programming the pic16c432 has a watchdog timer which is controlled by configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only, and is designed to keep the part in reset while the power supply stabilizes. there is also circuitry to reset the device if a brown-out occurs, which provides at least a 72 ms reset. with these three functions on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options. 9.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is beyond ? the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h ? 3fffh), which can be accessed only during programming.
pic16c432 ds41140c-page 44 preliminary ? 2000-2013 microchip technology inc. register 9-1: conf iguration word cp1 cp0 (2) cp1 cp0 (2) cp1 cp0 (2) ?boden (1) cp1 cp0 (2) pwrte (1) wdte f0sc1 f0sc0 bit 13 bit 0 bit 13-8 cp1:cp0 pairs: code protection bit pairs (2) bit 5-4 code protection for 2k program memory bits 11 = program memory code protection off 10 = 0400h-07ffh code protected 01 = 0200h-07ffh code protected 00 = 0000h-07ffh code protected bit 7 unimplemented : read as '1' bit 6 boden : brown-out reset enable bit (1) 1 = bod enabled 0 = bod disabled bit 3 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables powe r-up timer (pwrt), regardless of the value of bit pwrte. ensure the power-up timer is enabled anytime brown-out reset in enabled. 2: all of the cp<1:0> pairs have to be given the sa me value to enable the code protection scheme listed. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2000-2013 microchip technology inc. preliminary ds41140c-page 45 pic16c432 9.2 oscillator configurations 9.2.1 oscillator types the pic16c432 can be operated in four different oscillator options. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp - low power crystal ? xt - crystal/resonator ? hs - high speed crystal/resonator ? rc - resistor/capacitor 9.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation (figure 9-1). the pic16c432 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1 pin (figure 9-2). figure 9-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 9-2: exter nal clock input operation (hs, xt or lp osc configuration) table 9-1: ceramic resonators, pic16c432 table 9-2: capacitor selection for crystal oscillator, pic16c432 note 1: see table 9-1 and table 9-2 for recom- mended values of c1 and c2. 2: a series resistor may be required for at strip cut crystals. c1 c2 xtal osc2 r s osc1 rf sleep to internal logic pic16c432 note 2 clock from ext. system pic16c432 osc1 osc2 open ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. note 1: recommended values of c1 and c2 are indentical to the ranges tested table. 2: higher capacitance increases the stability of oscillator, but also increases the start- up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 4: rs may be required in hs mode, as well as xt mode, to avoid over driving crystals with low drive level specification.
pic16c432 ds41140c-page 46 preliminary ? 2000-2013 microchip technology inc. 9.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used, or a sim- ple oscillator circuit with ttl gates can be built. pre- packaged oscillators provide a wide operating range and better stability. a well designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. figure 9-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180 ? phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiometers bias the 74as04 in the linear region. this could be used for external oscillator designs. figure 9-3: external parallel resonant crystal oscillator circuit figure 9-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180 ? phase shift in a series resonant oscillator circuit. the 330 k ? resistors provide the negative feedback to bias the inverters in their linear region. figure 9-4: external series resonant crystal oscillator circuit 9.2.4 rc oscillator for timing insensitive applications, the ?rc? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 9-5 shows how the r/c combination is connected to the pic16c432. for r ext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (i.e., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, it is recommended to keep r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance, or package lead frame capacitance. the variation is larger for larger r (since leakage cur- rent variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see section 2.0 for variation of oscillator frequency due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin and can be used for test pur- poses, or to synchronize other logic (see figure 4-2 for waveform). figure 9-5: rc oscillator mode 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c432 clkin to other devices 330 74as04 74as04 pic16c432 clkin to o t h e r devices xtal 330 74as04 0.1 mf osc2/clkout c ext r ext v dd pic16c432 osc1 f osc /4 internal clock v dd
? 2000-2013 microchip technology inc. preliminary ds41140c-page 47 pic16c432 9.3 reset the pic16c432 differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt reset (normal operation) e) wdt wake-up (sleep) f) brown-out reset (bod) some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset, mclr reset, wdt reset and mclr reset during sleep. they are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in table 9-4 . these bits are used in soft- ware to determine the nature of the reset. see ta bl e 9 - 6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 9-6 . the mclr reset path has a noise filter to detect and ignore small pulses. see table 12-6 for pulse width specification. figure 9-6: simplified block di agram of on-chip reset circuit s r q external reset mclr / v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt timeout power-on reset ost pwrt chip_reset 10-bit ripple-counter reset enable ost enable pwrt sleep see table 9-3 for timeout situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden clkin pin v pp pin 10-bit ripple-counter
pic16c432 ds41140c-page 48 preliminary ? 2000-2013 microchip technology inc. 9.4 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost) and brown-out reset (bod) 9.4.1 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the por, just tie the mclr pin through a resistor to v dd . this will eliminate exter- nal rc components usually needed to create power-on reset. a maximum rise time for v dd is required. see electrical specifications for details. the por circuit does not produce an internal reset when v dd declines. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating condi- tions are met. for additional information, refer to application note an607, ?power-up trouble shooting?. 9.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms (nominal) timeout on power-up only, from por or brown-out reset. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte, can disable (if set), or enable (if cleared or programmed) the power-up timer. the power-up timer should always be enabled when brown-out reset is enabled. the power-up time delay will vary from chip-to-chip and due to v dd , temperature and process variation. see dc parameters for details. 9.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost timeout is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 9.4.4 brown-out reset (bod) the pic16c432 has an on-chip brown-out reset cir- cuitry. a configuration bit, boren, can disable (if clear/ programmed), or enable (if set) the brown-out reset circuitry. if v dd falls below 4.0v (refer to bv dd param- eter d005) for greater than parameter (t bor ) in table 12-6, the brown-out situation will reset the chip. a reset won?t occur if v dd falls below 4.0v for less than parameter (t bor ). on any reset (power-on, brown-out, watchdog, etc.), the chip will remain in reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above bv dd , the power-up timer will execute a 72 ms reset. the power-up timer should always be enabled when brown-out reset is enabled. figure 9-7 shows typical brown-out situations. figure 9-7: brown-o ut situations 72 ms bv dd v dd internal reset bv dd v dd internal reset 72 ms <72 ms 72 ms bv dd v dd internal reset
? 2000-2013 microchip technology inc. preliminary ds41140c-page 49 pic16c432 9.4.5 timeout sequence on power-up, the timeout sequence is as follows: first pwrt timeout is invoked after por has expired, then ost is activated. the total timeout will vary based on oscillator configuration and pwrte bit status. for example, in rc mode with pwrte bit erased (pwrt disabled), there will be no timeout at all. figure 9-8, figure 9-8 and figure 9-9 depict timeout sequences. since the timeouts occur from the por pulse, if mclr is kept low long enough, the timeouts will expire. then bringing mclr high will begin execution immediately (see figure 9-8). this is useful for testing purposes or to synchronize more than one pic ? device operating in parallel. table 9-5 shows the reset conditions for some spe- cial registers, while table 9-6 shows the reset condi- tions for all the registers. 9.4.6 power control (pcon)/status register the power control/status register, pcon (address 8eh), has two bits. bit0 is bor (brown-out). bor is unknown on power- on reset. it must then be set by the user and checked on subsequent resets to see if bor = 0, indicating that a brown-out has occurred. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown-out circuit is disabled (by setting boden bit = 0 in the configuration word). bit1 is por (power-on reset). it is a ?0? on power-on reset and unaffected otherwise. the user must write a ?1? to this bit following a power-on reset. on a subse- quent reset, if por is ?0?, it will indicate that a power- on reset must have occurred (v dd may have gone too low). table 9-3: timeout in various situations table 9-4: status/pcon bits and their significance oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms ? 72 ms ? por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 10xx brown-out reset 110u wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep legend: x = unknown, u = unchanged
pic16c432 ds41140c-page 50 preliminary ? 2000-2013 microchip technology inc. table 9-5: initialization condition for special registers table 9-6: initialization condition for registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 uuuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 000x xuuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?. note 1: when the wake-up is due to an interrupt and global enable bit gie is set, the pc is loaded with the inter- rupt vector (0004h) after execution of pc+1. register address power-on reset mclr reset during normal operation mclr reset during sleep wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt timeout w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h ? - - tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000 0000 0000 0000 pc + 1 (3) status 03h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h ---x xxxx ---u uuuu ---u uuuu portb 06h xxxx xxxx uuuu uuuu uuuu uuuu cmcon 1fh 00-- 0000 00-- 0000 uu-- uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uqqq (2) pir1 0ch -0-- ---- -0-- ---- -q-- ---- (2,5) option 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu pie1 8ch -0-- ---- -0-- ---- -u-- ---- pcon 8eh ---- --0x ---- --uq (1,6) ---- --uu linintf 90h ---- -111 ---- -1-1 ---- -1-1 vrcon 9fh 000- 0000 000- 0000 uuu- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 9-5 for reset value for specific conditions. 5: if wake-up was due to comparator input changing , then bit 6 = 1 . all other interrupts generating a wake- up will cause bit 6 = u . 6: if reset was due to brown-out, then pcon bit0 = 0 . all other resets will cause bit0 = u .
? 2000-2013 microchip technology inc. preliminary ds41140c-page 51 pic16c432 figure 9-8: timeout sequence on power-up (mclr not tied to v dd ): case 1 figure 9-9: timeout sequence on power-up (mclr not tied to v dd ): case 2 figure 9-10: timeout sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt timeout ost timeout internal reset v dd mclr internal por pwrt timeout ost timeout internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt timeout ost timeout internal reset
pic16c432 ds41140c-page 52 preliminary ? 2000-2013 microchip technology inc. figure 9-11: external power-on reset circuit (for slow v dd power-up) figure 9-12: exte rnal brown-out protection circuit 1 figure 9-13: external brown-out protection circuit 2 figure 9-14: external brown-out protection circuit 3 note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: < 40 k ? is recommended to make sure that voltage drop across r does not violate the device?s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flow- ing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown due to electrostatic discharge (esd), or electrical overstress (eos). c r1 r d v dd mclr pic16c432 v dd note 1: this circuit will activate reset when v dd goes below (vz + 0.7v), where vz = zener voltage. 2: internal brown-out reset circuitry should be disabled when using this circuit. v dd 33k 10k 40k pic16c432 v dd mclr note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: ? ? ? 2: internal brown-out detection should be dis- abled when using this circuit. 3: resistors should be adjusted for the charac- teristics of the transistor. v dd x r1 r1 + r2 = 0.7v v dd r2 40k pic16c432 r1 q1 v dd mclr t his brown-out protection circuit employs microchip technology?s mcp809 microcontroller supervisor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collector outputs with both high and low active reset pins. there are 7 different trip point selections to accommodate 5v and 3v systems. mclr pic16c432 v dd v ss rst mcp809 v dd v dd bypass capacitor
? 2000-2013 microchip technology inc. preliminary ds41140c-page 53 pic16c432 9.5 interrupts the pic16c432 has 4 sources of interrupt: ? external interrupt rb0/int ? tmr0 overflow interrupt ? portb change interrupts (pins rb<7:4>) ? comparator interrupt ? lin bus wake-up can be wired to rb0, or compar- ator the interrupt control register (intcon) and the periph- eral interrupt register (pir1) record individual interrupt requests in flag bits. intcon and pir1 have individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts, or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. gie is cleared on reset. the ?return from interrupt? instruction, retfie , exits interrupt routine, as well as sets the gie bit, which re- enables all unmasked interrupts. the int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flag is contained in the special register pir1. the corresponding interrupt enable bit is contained in special registers pie1. when an interrupt is responded to, the gie is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid rb0/int recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends on when the interrupt event occurs (figure 9- 16). the latency is the same for one or two cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. figure 9-15: interrupt logic note 1: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the cpu will execute a nop in the cycle immediately following the instruction which clears the gie bit. the interrupts which were ignored are still pending to be serviced when the gie bit is set again. rbif rbie t0if t0ie intf inte gie peie wake-up (if in sleep mode) interrupt to cpu cmie cmif
pic16c432 ds41140c-page 54 preliminary ? 2000-2013 microchip technology inc. 9.5.1 rb0/int interrupt external interrupt on rb0/int pin is edge triggered; either rising if intedg bit (option<6>) is set, or fall- ing, if intedg bit is clear. when a valid edge appears on the rb0/int pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing the inte control bit (intcon<4>). the intf bit must be cleared in software in the interrupt service routine before re- enabling this interrupt. the rb0/int interrupt can wake-up the processor from sleep, if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up. see section 9.8 for details on sleep and figure 9-18 for timing of wake- up from sleep through rb0/int interrupt. 9.5.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. for operation of the timer0 module, see section 6.0. 9.5.3 portb interrupt an input change on portb <7:4> sets the rbif (intcon<0>) bit. the interrupt can be enabled/dis- abled by setting/clearing the rbie (intcon<4>) bit. for operation of portb (section 4.2). 9.5.4 comparator interrupt see section 7.6 for complete description of comparator interrupts. figure 9-16: int pin interrupt timing note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may not get set. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 2 3 note 1: intf flag is sampled here (every q1). 2: interrupt latency = 1-4 tcy where tcy = instruction cycle ti me. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set any time during the q4-q1 cycles.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 55 pic16c432 9.6 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w register and status register). this will have to be implemented in software. example 9-7 stores and restores the status and w registers. the user register, w_temp, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., w_temp is defined at 0x70 in bank 0 and it must also be defined at 0xf0 in bank 1). the user register, status_temp, must be defined in bank 0. the example 9-7: ? stores the w register ? stores the status register in bank 0 ? executes the isr code ? restores the status (and bank select bit ? register) ? restores the w register example 9-7: saving the status and w registers in ram movw f w_temp ;copy w to temp register, ;could be in either bank swap f status,w ;swap status to be saved into w bcf status,rp0 ;change to bank 0 regard- less ;of current bank movw f status_temp ;save status to bank 0 ;register : : (isr) : swap f status_temp ,w ;swap status_temp regis- ter ;into w, sets bank to original ;state movw f status ;move w into status regis- ter swap f w_temp,f ;swap w_temp swap f w_temp,w ;swap w_temp into w
pic16c432 ds41140c-page 56 preliminary ? 2000-2013 microchip technology inc. 9.7 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator which does not require any external components. this rc oscillator is separate from the rc oscillator of the clkin pin. that means that the wdt will run even if the clock on the osc1 and osc2 pins of the device have been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt timeout generates a device reset. if the device is in sleep mode, a wdt timeout causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming the con- figuration bit wdte as clear (section 9.1). 9.7.1 wdt period the wdt has a nominal timeout period of 18 ms, (with no prescaler). the timeout periods vary with tempera- ture, v dd and process variations from part to part (see dc specs). if longer timeout periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control, by writing to the option register. thus, timeout periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer timeout. 9.7.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt timeout occurs. figure 9-17: watchdog timer block diagram table 9-8: summary of watchdog timer registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits ? boren cp1 cp0 pwrte wdte fosc1 fosc0 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: _ = unimplemented location, read as ?0?, + = reserved for future use note 1: shaded cells are not used by the watchdog timer. from tmr0 clock source ? (figure 6-6) to tmr0 (figure 6-6) postscaler watchdog timer m u x psa 8 - to -1 mux psa wdt timeout 1 0 0 1 wdt enable bit ps<2:0> ? ? note 1: t0se, t0cs, psa, ps<2:0> are bits in the option register. 8 mux
? 2000-2013 microchip technology inc. preliminary ds41140c-page 57 pic16c432 9.8 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit in the status register is cleared, the to bit is set and the oscillator driver is turned off. the i/o ports maintain the status they had before sleep was executed (driving high, low, or hi- impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd or v ss , with no external circuitry drawing current from the i/o pin, and the com- parators and v ref should be disabled. i/o pins that are hi-impedance inputs should be pulled high or low exter- nally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 9.8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from rb0/int pin, rb port change, or the peripheral interrupt (comparator). 4. lin activity. the first event will cause a device reset. the two lat- ter events are considered a continuation of program execution. the to and pd bits in the status register can be used to determine the cause of device reset. pd bit, which is set on power-up is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the correspond- ing interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. note: it should be noted that a reset generated by a wdt timeout does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from sleep. the sleep instruction is completely executed.
pic16c432 ds41140c-page 58 preliminary ? 2000-2013 microchip technology inc. figure 9-18: wake-up from sleep through interrupt 9.9 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 9.10 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. only the least significant 4 bits of the id locations are used. 9.11 in-circuit serial programming the pic16c432 microcontroller can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x/9xx programming specifications (liter- ature #ds30228). a typical in-circuit serial programming connection is shown in figure 9-19. figure 9-19: typical in-circuit serial programming connection q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay does not occur for rc osc mode. 3: gie = '1' assumed. in this case after wake-up, the processor jumps to the interrupt routine. if gie = '0', execution will conti nue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code protecting windowed devices. external connector signals to n o r m a l connections to n o r m a l connections pic16c432 v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
? 2000-2013 microchip technology inc. preliminary ds41140c-page 59 pic16c432 10.0 instruction set summary each pic16c432 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16c432 instruction set summary in table 10-2 lists byte-oriented , bit- oriented , and literal and control operations. table 10-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight- or eleven-bit constant, or literal value. table 10-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. table 10-1 lists the instructions recognized by the mpasm assembler. figure 10-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 label label name tos top-of-stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to timeout bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier) note: to maintain upward compatibility with future pic ? products, do not use the option and tris instructions.
pic16c432 ds41140c-page 60 preliminary ? 2000-2013 microchip technology inc. figure 10-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
? 2000-2013 microchip technology inc. preliminary ds41140c-page 61 pic16c432 table 10-2: pic16c432 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1(2) 1(2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf portb, 1) the value used will be that value present on the pins themselves. for example, if t he data latch is ?1? for a pin configured as input and is driven low by an external device, the data will be written back with a ?0?. 2: if this instruction is executed on the tmr0 register ( and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second is exe- cuted as a nop .
pic16c432 ds41140c-page 62 preliminary ? 2000-2013 microchip technology inc. 10.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w regis- ter. words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w=0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?ed with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example andwf fsr, 1 before instruction w=0x17 fsr = 0xc2 after instruction w=0x17 fsr = 0x02
? 2000-2013 microchip technology inc. preliminary ds41140c-page 63 pic16c432 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0', then the next instruction is skipped. if bit 'b' is '0', then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two- cycle instruction. words: 1 cycles: 1 (2) example here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address here after instruction if flag<1>= 0, ? pc = address true if flag<1>=1, pc = address false
pic16c432 ds41140c-page 64 preliminary ? 2000-2013 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two- cycle instruction. words: 1 cycles: 1 (2) example here false true btfss goto ? ? ? flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, ? pc = address false if flag<1> = 1, ? pc = address true call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc) + 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. words: 1 cycles: 2 example here call there before instruction pc = address here after instruction pc = address there tos = address here +1 clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z = 1
? 2000-2013 microchip technology inc. preliminary ds41140c-page 65 pic16c432 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0000 0011 description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z = 1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler = 0 to = 1 pd = 1 comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z = 0 after instruction cnt = 0x00 z = 1
pic16c432 ds41140c-page 66 preliminary ? 2000-2013 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1 (2) example here decfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt? 0, pc = address here+1 goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in regis- ter 'f'. words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z = 0 after instruction cnt = 0x00 z = 1
? 2000-2013 microchip technology inc. preliminary ds41140c-page 67 pic16c432 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in regis- ter 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1 (2) example here incfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt + 1 if cnt = 0, pc = address continue if cnt ? 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register are or?ed with the eight bit literal 'k'. the result is placed in the w reg- ister. words: 1 cycles: 1 example iorl w 0x35 before instruction w = 0x9a after instruction w = 0xbf z = 1 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .or. (f) ? (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with register 'f'. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in regis- ter 'f'. words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z = 1
pic16c432 ds41140c-page 68 preliminary ? 2000-2013 microchip technology inc. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register. the don?t cares will assemble as 0?s. words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z = 1 movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to regis- ter 'f'. words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop
? 2000-2013 microchip technology inc. preliminary ds41140c-page 69 pic16c432 option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code compatibility with pic16c5x prod- ucts. since option is a readable/ writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibil- ity with future pic ? products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global inter- rupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example table call table ;w contains table ;offset value ? ;w now has table value ? ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos
pic16c432 ds41140c-page 70 preliminary ? 2000-2013 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in regis- ter 'f'. words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c = 0 after instruction reg1 = 1110 0110 w = 1100 1100 c = 1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. words: 1 cycles: 1 example rrf reg1,0 before instruction reg1 = 1110 0110 c = 0 after instruction reg1 = 1110 0110 w = 0111 0011 c = 0 sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. timeout status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 9.8 for more details. words: 1 cycles: 1 example: sleep register f c
? 2000-2013 microchip technology inc. preliminary ds41140c-page 71 pic16c432 sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ? k ? 255 operation: k - (w) ? (w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s complement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w= 1 c=? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c= ? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c=? after instruction w= 0xff c = 0; result is negative subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - (w) ? (dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in reg- ister 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative
pic16c432 ds41140c-page 72 preliminary ? 2000-2013 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>), (f<7:4>) ? (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w register. if 'd' is 1, the result is placed in regis- ter 'f'. words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibil- ity with future pic ? products, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ? k ? 255 operation: (w) .xor. k ? (w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorl w 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .xor. (f) ? (dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example xorw f reg 1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
? 2000-2013 microchip technology inc. preliminary ds41140c-page 73 pic16c432 11.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ ? mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development ? programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 11.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (auto- matically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 11.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 11.3 mplab c17 and mplab c18 ? c compilers the mplab c17 and mplab c18 code development systems are complete ansi ?c? compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c432 ds41140c-page 74 preliminary ? 2000-2013 microchip technology inc. 11.4 mplink object linker/ ? mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 11.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 11.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 11.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 75 pic16c432 11.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic mcus and can be used to develop for this and other pic microcontrollers. the mplab icd utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 11.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 11.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 11.11 picdem 1 low cost pic mcu ? demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip?s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 11.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c432 ds41140c-page 76 preliminary ? 2000-2013 microchip technology inc. 11.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 11.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 11.15 k ee l oq evaluation and ? programming tools k ee l oq evaluation and programming tools support microchip?s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 77 pic16c432 table 11-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment ??????????????? mplab ? c17 c compiler ?? mplab ? c18 c compiler ?? mpasm tm assembler/ ? mplink tm object linker ??????????????? ? ? emulators mplab ? ice in-circuit emulator ??? ? ?? ** ????????? icepic tm in-circuit emulator ? ??? ??? ? debugger mplab ? icd in-circuit debugger ? * ? * ?? programmers picstart ? plus entry level development programmer ??? ? ?? ** ????????? pro mate ? ii ? universal device programmer ??? ? ?? ** ????????? ? ? demo boards and eval kits picdem tm 1 demonstration board ??? ? ?? picdem tm 2 demonstration board ? ? ? ? ?? picdem tm 3 demonstration board ? picdem tm 14a demonstration board ? picdem tm 17 demonstration board ? k ee l oq ? evaluation kit ? k ee l oq ? transponder kit ? microid tm programmer?s kit ? 125 khz microid tm ? developer?s kit ? 125 khz anticollision microid tm developer?s kit ? 13.56 mhz anticollision ? microid tm developer?s kit ? mcp2510 can developer?s kit ? * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ?
pic16c432 ds41140c-page 78 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 79 pic16c432 12.0 electrical specifications absolute maximum ratings ? ambient temperature under bias ................................................................................................. ...........-40 ? to +125 ? c storage temperature ............................................................................................................ ..................-65 ? to +150 ? c voltage on any pin with respect to v ss (except v dd and mclr ) ....................................................-0.6v to v dd +0.6v voltage on v dd with respect to v ss ............................................................................................................. 0 to +7.0v voltage on ra4 with respect to v ss ........................................................................................................................ 8.5v voltage on mclr with respect to v ss (note 2) ..............................................................................................0 to +14v voltage on ra4 with respect to v ss ........................................................................................................................ 8.5v voltage on lin with respect to v ss .......................................................................................................................... 40v total power dissipation (note 1) ........................................................................................................................... 1.0 w maximum current out of v ss pin ....................................................................................................................... 300 ma maximum current into v dd pin .......................................................................................................................... 2 50 ma input clamp current by lin pin, iik (v i <0 or v i > v bat ...................................................................................... 200 ma output clamp current by lin pin, iok (v o <0 or v o > v bat ) ............................................................................. 200 ma input clamp current, i ik (v i <0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? 20 ma output clamp current, i ok (v o <0 or v o >v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin (source by v dd ) .......................................................................... 25 ma maximum current sourced by any i/o pin (source by v dd ) ................................................................................. 25 ma maximum current sunk by porta and portb (source by v dd ) ..................................................................... 200 ma maximum current sourced by porta and portb (source by v dd ) ................................................................ 200 ma maximum current sunk by lin pin (source by v bat )......................................................................................... 200 ma maximum current sunk by bact pin (source by v bat )...................................................................................... 1.8 ma note 1: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latchup. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr pin, rather than pulling this pin directly to v ss . ? notice : stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c432 ds41140c-page 80 preliminary ? 2000-2013 microchip technology inc. figure 12-1: pic16c432 volt age-frequency graph, -40 ? c ? t a ? +125 ? c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 81 pic16c432 12.1 dc characteristics: pic16c432 (industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 ? c ?? t a ? +85 ? c for industrial and -40 ? c ? t a ? +125 ? c for extended param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 4.5 ? 5.5 v see figure 12-1 through figure 12-3 d001a v bat battery supply voltage 8.0 13.8 18 v d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage ? to ensure power-on reset ?v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate ? to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d005 v bor brown-out detect voltage 3.7 4.0 4.35 v boren configuration bit is cleared i dd supply current (2), (4) d010 ? ? ? 1.2 4.0 4.0 2.0 6.0 7.0 ma ma ma f osc = 4 mhz, v dd = 5.5v, wdt disabled, ? xt osc mode, (4) * f osc = 20 mhz, v dd = 4.5v, wdt disabled, hs osc mode f osc = 20 mhz, v dd = 5.5v, wdt disabled*, ? hs osc mode i pd power-down current (3) d020 ? ? ? ? ? ? 5.0 9.0 15 ? a ? a ? a v dd = 4.5v* v dd = 5.5v v dd = 5.5v extended d313 ? i dd - lin lin transceiver current (5) 1 ma lin xcvr enabled ? i wdt wdt current (5) d022 ? 6.0 10 12 ? a ? a v dd = 4.0v (125 ? c) d022a ? i bor brown-out reset current (5) ? 75 125 ? abod enabled, v dd = 5.0v d023 ? i comp comparator current for each comparator (5) ?3060 ? av dd = 4.0v d023a ? i vref v ref current (5) ? 80 135 ? av dd = 4.0v * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switc h- ing rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. ? the test conditions for all i dd measurements in active operation mode are: ? osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , ? mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 5: the ? current is the additional current cons umed when this peripheral is enabled. th is current should be added to the base i dd or i pd measurement. 6: commercial temperature range only.
pic16c432 ds41140c-page 82 preliminary ? 2000-2013 microchip technology inc. 12.2 dc characteristics: pic16c432 (industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? ta ? +85c for industrial and -40c ? ta ? +125c for extended operating voltage v dd range as described in dc spec table 12.3 parm no. sym characteristic min typ? max unit conditions v il input low voltage i/o ports d030 with ttl buffer v ss ?0.8v 0.15 v dd vv dd = 4.5v to 5.5v, otherwise d031 with schmitt trigger input v ss 0.2 v dd v d032 mclr , ra4/t0cki,osc1 ? (in rc mode) v ss ? 0.2 v dd v (note 1) d033 osc1 (in xt and hs) osc1 (in lp) v ss v ss ? ? 0.3 v dd 0.6 v dd - 1.0 v v d034 v il _ lin low level input voltage -8 ? 0.4 v bat v dominant state v ih input high voltage i/o ports d040 with ttl buffer 2.0v .25 v dd + 0.8v ?v dd v dd vv dd = 4.5v to 5.5v d041 with schmitt trigger input 0.8 v dd v dd d042 mclr ra4/t0cki 0.8 v dd ?v dd v d043 d043a osc1 (xt, hs and lp) osc1 (in rc mode) 0.7 v dd 0.9 v dd ?v dd v (note 1) d044 v ih _ lin high level input voltage 0.6 v bat ? 18 v recessive state d070 i purb portb weak pull-up current 50 200 400 ? av dd = 5.0v, v pin = v ss i il input leakage current (2), (3) i/o ports (except porta) 1.0 ? av ss ? v pin ? v dd , pin at hi-impedance d060 porta ? ? 0.5 ? a vss ? v pin ? v dd , pin at hi-impedance d061 ra4/t0cki ? ? 1.0 ? a vss ? v pin ? v dd d063 osc1, mclr ??5.0 ? a vss ? v pin ? v dd , xt, hs and lp osc configuration d064 i oh _ lin high level output leakage current ? ? 20 ? av bus ?? v bat ; v bus < 40v v ol output low voltage d080 i/o ports ? ? 0.6 v i ol =8.5 ma, v dd =4.5v, -40 ? to +85 ? c ??0.6vi ol =7.0 ma, v dd =4.5v, +125 ? c d083 osc2/clkout (rc only) ? ? 0.6 v i ol =1.6 ma, v dd =4.5v, -40 ? to +85 ? c ??0.6vi ol =1.2 ma, v dd =4.5v, +125 ? c d084 bact ? ? tbd tbd d085 v ol _ lin low level output voltage ? 0.2 v bat vi ol = 200 ma v bus = 12v v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 ? ? v i oh =-3.0 ma, v dd =4.5v, -40 ? to +85 ? c v dd -0.7 ? ? v i oh =-2.5 ma, v dd =4.5v, +125 ? c d092 osc2/clkout (rc only) v dd -0.7 ? ? v i oh =-1.3 ma, v dd =4.5v, -40 ? to +85 ? c v dd -0.7 ? ? v i oh =-1.0 ma, v dd =4.5v, +125 ? c d093 v oh bact 4.0v ? ? v v bat = 18v, v dd = 5.0v, i oh = 1.8 ma d094 v oh _ lin high level output voltage 0.8 v bat ?v d150* v od open-drain high voltage 8.5 v ra4 pin * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmitt tri gger input. it is not recommended that the pic16c432 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: lin tested 4 mhz, 14.4v v bat , 5.0v v dd .
? 2000-2013 microchip technology inc. preliminary ds41140c-page 83 pic16c432 12.3 lin transceiver bus interface specifications capacitive loading specs on ? output pins d100 c osc 2 osc2 pin 15* pf in xt, hs and lp modes when external clock used to drive osc1 100a c lin lin (4) 10* nf 100b c bact bact 50* pf d101 c io all i/o pins/osc2 (in rc mode) 50* pf 12.2 dc characteristics: pic16c432 (industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? ta ? +85c for industrial and -40c ? ta ? +125c for extended operating voltage v dd range as described in dc spec table 12.3 parm no. sym characteristic min typ? max unit conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmitt tri gger input. it is not recommended that the pic16c432 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: lin tested 4 mhz, 14.4v v bat , 5.0v v dd . operating conditions: v dd range as described in table 12-1, -40 ? c pic16c432 ds41140c-page 84 preliminary ? 2000-2013 microchip technology inc. 12.4 comparator specifications 12.5 voltage reference specifications. 12.6 lin transceiver operating specifications. operating conditions: v dd range as described in table 12-1, -40 ? c transitions from 0000 to 1111 . operating conditions: v dd range as described in table 12-1, -40 ? c ? 2000-2013 microchip technology inc. preliminary ds41140c-page 85 pic16c432 12.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 12-2: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp ck clkout osc osc1 io i/o port t0 t0cki mc mclr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 and lin bus 15 pf for osc2 output 10 nf for lin load condition 1 load condition 2
pic16c432 ds41140c-page 86 preliminary ? 2000-2013 microchip technology inc. 12.8 timing diagrams and specifications figure 12-3: extern al clock timing table 12-1: external clock timing requirements param no. sym characteristic min typ? max units conditions 1a fosc external clkin frequency (1) dc ? 4 mhz xt and rc osc mode, v dd =5.0v dc ? 20 mhz hs osc mode dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4 mhz rc osc mode, v dd =5.0 ov 0.1 ? 4 mhz xt osc mode 1 ? 20 mhz hs osc mode dc ? 200 khz lp osc mode 1tosc external clkin period (1) 250 ? ? ns xt and rc osc mode 50 ? ? ns hs osc mode 5 ? ? ms lp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 5 ? ? ms lp osc mode 2tcy instruction cycle time (1) 200 ? dc ns t cy =f osc /4 3* tosl, to s h external clock in (osc1) high or low time 100* ? ? ns xt oscillator, t osc l/h duty cycle 2* ? ? ms lp oscillator, t osc l/h duty cycle 20* ? ? ns hs oscillator, t osc l/h duty cycle 4* tosr, to sf external clock in (osc1) rise or fall time 25* ? ? ns xt oscillator 50* ? ? ns lp oscillator 15* ? ? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these paramete rs are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type, under standard operating condition s with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1 pin. ? when an external clock input is used, the "max." c ycle time limit is "dc" (no clock) for all devices . osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 2000-2013 microchip technology inc. preliminary ds41140c-page 87 pic16c432 figure 12-4: clko ut and i/o timing table 12-2: clkout and i/o timing requirements param no. sym characteristic min typ? max units 10* tosh2ckl osc1 ? to clkout ?? (1) ? 75 200 ns 11* tosh2ckh osc1 ? to clkout ? (1) ? 75 200 ns 12* tckr clkout rise time (1) ? 35 100 ns 13* tckf clkout fall time (1) ? 35 100 ns 14* tckl2iov clkout ? to port out valid (1) ? ? 20 ns 15* tiov2ckh port in valid before clkout ? (1) t osc +200 ns ? ? ns 16* tckh2ioi port in hold after clkout ? (1) 0??ns 17* tosh2iov osc1 ? (q1 cycle) to port out valid ? 50 150 ns 18* tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19* tiov2osh port input valid to osc1 ? (i/o in setup time) 0 ? ? ns 20* tior port output rise time ? 10 40 ns 21* tiof port output fall time ? 10 40 ns 22* tinp rb0/int pin high or low time 25 ? ? ns 23 trbp rb<7:4> change interrupt high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these paramete rs are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 22 23 note 1: all tests must be done with specified capacitance loads (figure 12-2) 50 pf on i/o pins and clkout. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c432 ds41140c-page 88 preliminary ? 2000-2013 microchip technology inc. figure 12-5: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 12-6: brown-out reset timing table 12-3: reset, watchdog timer, oscillator start-up timer and power-up timer requirements param no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2000 ? ? ns -40 ? to +85 ? c 31 twdt watchdog timer timeout period (no prescaler) 7* 18 33* ms v dd = 5.0v, -40 ? to +85 ? c 32 tost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33 tpwrt power-up timer period 28* 72 132* ms v dd = 5.0v, -40 ? to +85 ? c 34 t ioz i/o hi-impedance from mclr low ? 2.0 ms 35 t bor brown-out reset pulse width 100* ? ? ms 3.7v ? v dd ? 4.3v * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameter s are for design guidance only and are not tested. v dd mclr internal por pwrt timeout osc timeout internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 v dd bv dd 35
? 2000-2013 microchip technology inc. preliminary ds41140c-page 89 pic16c432 figure 12-7: timer0 clock timing table 12-4: timer0 clock requirements table 12-5: lin ac characteristics parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period t cy + 40 * n ? ? ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. symbol parameter min. typ. max. unit note ? dv/dt ? slope rising and falling edges 1 2 3 v/ ? s (note 1) t trans_pd propagation delay of transmitter 4 ? st trans_pd = max(t trans_pdr or t trans_pdf ) t rec_pd propagation delay of receiver 6 ? st rec_pd = max (t rec_pdr or t rec_pdf ) t rec_sym symmetry of receiver propaga- tion delay rising edge w.r.t. fall- ing edge -2 2 ? st rec_sym = t rec_pdf - t rec_pdr t trans_sym symmetry of transmitter propa- gation delay rising edge w.r.t. falling edge -2 2 ? st trans_sym = t trans_pdf - t rans_pdr note 1: rising edge is system dependent. value is characterized but not tested. 41 42 40 ra4/t0cki tmr0
pic16c432 ds41140c-page 90 preliminary ? 2000-2013 microchip technology inc. table 12-6: lin thermal characteristics figure 12-8: timing diagram symbol parameter typ. max. unit note ? recovery recovery temperature +135 c information parameter ? shutdown shutdown temperature +155 c information parameter t therm thermal recovery time 1.5 ms information parameter txd (input of physical layer) t trans_pdf t trans_pdr bus signal rec. threshold rec. threshold t rec_pdf t rec_pdr rxd (physical layer output)
? 2000-2013 microchip technology inc. preliminary ds41140c-page 91 pic16c432 13.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs and tables, the data presented is outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. ?typical? represents the mean of the distribution at 25 ? c. ?max? or ?min? represents ? (mean + 3 ? ) or (mean - 3 ? ) respectively, where ?? is standard deviation, over the whole temperature range. figure 13-1: lin transceiver shutdown hysteresis (v) vs. temperature ( ? c) 20 18 16 14 12 10 8 6 4 2 0 115 120 125 130 135 140 145 150 155 vlin (v) v bat = 18.0v v dd = 5.0v txd = 0v temp (shutdown) temp (recover) temperature ( ? c) 120 135.2 143.1 135.2 143.1 150.0
pic16c432 ds41140c-page 92 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 93 pic16c432 14.0 packaging information 14.1 package marking information 20-lead cerdip windowed xxxxxxxxxxx yywwnnn xxxxxxxxxxx 20-lead ssop pic16c432 0007cbp -i/218 example 20-lead pdip example 0007cbp pic16c432/p301 xxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxx example 0007cbp pic16c432/p301 legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
pic16c432 ds41140c-page 94 preliminary ? 2000-2013 microchip technology inc. 20-lead ceramic dual in-line with window (jw) - 300 mil (cerdip) package drawing not available at this time.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 95 pic16c432 20-lead plastic shrink small outline (ss) - 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 f foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c b f a a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c432 ds41140c-page 96 preliminary ? 2000-2013 microchip technology inc. 20-lead plastic dual in-line (p) - 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.65 1.52 1.40 .065 .060 .055 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.56 3.30 3.05 .140 .130 .120 l tip to seating plane 26.42 26.24 26.04 1.040 1.033 1.025 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.87 7.49 .325 .310 .295 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c ? eb e ? p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-019 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2000-2013 microchip technology inc. preliminary ds41140c-page 97 pic16c432 appendix a: code for lin communication please check our web site at www.microchip.com for code availability. appendix b: revision history revision c (january 2013) added a note to each package outline drawing.
pic16c432 ds41140c-page 98 preliminary ? 2000-2013 microchip technology inc. notes:
? 2000-2013 microchip technology inc. preliminary ds41140c-page 99 pic16c432 index a addlw instruction ............................................................. 62 addwf instruction ............................................................. 62 andlw instruction ............................................................. 62 andwf instruction ............................................................. 62 assembler mpasm assembler ..................................................... 73 b bcf instruction ................................................................... 63 block diagram timer0....................................................................... 27 tmr0/wdt prescaler .......................................... 30 brown-out detect (bod) ..................................................... 48 bsf instruction ................................................................... 63 btfsc instruction............................................................... 63 btfss instruction ............................................................... 64 c call instruction ................................................................. 64 clrf instruction ................................................................. 64 clrw instruction ................................................................ 65 clrwdt instruction ........................................................... 65 cmcon register ................................................................ 33 code protection .................................................................. 58 comf instruction ................................................................ 65 comparator configuration................................................... 33 comparator interrupts ......................................................... 39 comparator module ............................................................ 33 comparator operation ........................................................ 35 comparator reference ....................................................... 35 configuration bits................................................................ 43 configuring the voltage reference ..................................... 41 crystal operation ................................................................ 45 d data memory organization ................................................... 7 decf instruction................................................................. 65 decfsz instruction ............................................................ 66 development support ......................................................... 73 e errata .................................................................................... 2 external crystal oscillator circuit ....................................... 46 g general purpose register file.............................................. 7 goto instruction ................................................................ 66 i i/o ports .............................................................................. 17 i/o programming considerations........................................ 22 icepic in-circuit emulator ................................................. 74 id locations ........................................................................ 58 incf instruction .................................................................. 66 incfsz instruction ............................................................. 67 in-circuit serial programming ............................................. 58 indirect addressing, indf and fsr registers ................... 16 instruction set addlw ....................................................................... 62 addwf....................................................................... 62 andlw ....................................................................... 62 andwf....................................................................... 62 bcf ............................................................................ 63 bsf............................................................................. 63 btfsc........................................................................ 63 btfss ........................................................................ 64 call........................................................................... 64 clrf .......................................................................... 64 clrw ......................................................................... 65 clrwdt .................................................................... 65 comf ......................................................................... 65 decf.......................................................................... 65 decfsz ..................................................................... 66 goto ......................................................................... 66 incf ........................................................................... 66 incfsz....................................................................... 67 iorlw ........................................................................ 67 iorwf........................................................................ 67 movf ......................................................................... 68 movlw ...................................................................... 68 movwf...................................................................... 68 nop............................................................................ 68 option...................................................................... 69 retfie....................................................................... 69 retlw ....................................................................... 69 return..................................................................... 69 rlf............................................................................. 70 rrf ............................................................................ 70 sleep ........................................................................ 70 sublw ....................................................................... 71 subwf....................................................................... 71 swapf ....................................................................... 72 tris ........................................................................... 72 xorlw....................................................................... 72 xorwf ...................................................................... 72 instruction set summary .................................................... 59 int interrupt ....................................................................... 54 intcon register................................................................ 12 interrupts ............................................................................ 53 iorlw instruction .............................................................. 67 iorwf instruction .............................................................. 67 k k ee l oq evaluation and programming tools...................... 76 l lin hardware interface....................................................... 23 lin interfacing .................................................................... 23 lin protocol ........................................................................ 23 lin transceiver .................................................................. 23 m movf instruction................................................................ 68 movlw instruction............................................................. 68 movwf instruction ............................................................ 68 mplab c17 and mplab c18 c compilers ....................... 73 mplab icd in-circuit debugger ........................................ 75 mplab ice high performance universal in-circuit emulator with mplab ide ................................................................. 74 mplab integrated development environment software.... 73 mplink object linker/mplib object librarian .................. 74 n nop instruction .................................................................. 68 o one-time-programmable (otp) devices ............................ 5
pic16c432 ds41140c-page 100 preliminary ? 2000-2013 microchip technology inc. option instruction............................................................. 69 option register ................................................................ 11 oscillator configurations ..................................................... 45 oscillator start-up timer (ost) .......................................... 48 p package marking information ............................................. 93 packaging information ........................................................ 93 pcl and pclath ............................................................... 15 pcon register ................................................................... 14 picdem 1 low cost pic mcu demonstration board ........ 75 picdem 17 demonstration board ...................................... 76 picdem 2 low cost pic16cxx demonstration board...... 75 picdem 3 low cost pic16cxxx demonstration board ... 76 picstart plus entry level development programmer .... 75 pie1 register ...................................................................... 13 pir1 register...................................................................... 13 port rb interrupt ................................................................. 54 porta................................................................................ 17 portb................................................................................ 20 power control/status register (pcon) .............................. 49 power-down mode (sleep) ............................................... 57 power-on reset (por) ....................................................... 48 timeout (to bit).......................................................... 10 power-up timer (pwrt)..................................................... 48 prescaler ............................................................................. 30 program memory organization ............................................. 7 q quick-turn-programming (qtp) devices ............................. 5 r rc oscillator ....................................................................... 46 reset ................................................................................ 47 retfie instruction.............................................................. 69 retlw instruction .............................................................. 69 return instruction............................................................ 69 rlf instruction.................................................................... 70 rrf instruction ................................................................... 70 s serialized quick-turn-programming (sqtp) devices.......... 5 sleep instruction ............................................................... 70 software simulator (mplab sim)....................................... 74 special features of the cpu............................................... 43 special function registers ................................................... 8 stack ................................................................................... 15 status register dc bit.......................................................................... 10 irp bit......................................................................... 10 to bit .......................................................................... 10 z bit............................................................................. 10 status register.................................................................... 10 sublw instruction.............................................................. 71 subwf instruction.............................................................. 71 swapf instruction.............................................................. 72 t thermal shutdown .............................................................. 23 timer0 timer0 ....................................................................... 27 timer0 (tmr0) interrupt ........................................... 27 timer0 (tmr0) module ............................................. 27 tmr0 with external clock........................................... 29 timer1 switching prescaler assignment ................................ 31 timing diagrams and specifications .................................. 86 tmr0 interrupt.................................................................... 54 tris instruction .................................................................. 72 trisa ................................................................................. 17 trisb ................................................................................. 20 v voltage reference module ................................................. 41 vrcon register ................................................................ 41 w watchdog timer (wdt)...................................................... 56 www, on-line support ......... .............................................. 2 x xorlw instruction ............................................................. 72 xorwf instruction............................................................. 72
? 2000-2013 microchip technology inc. ds41140c-page 101 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
ds41140c-page 102 ? 2000-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41140c 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2000-2013 microchip technology inc. preliminary ds41140c-page 103 pic16c432 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device c onfiguration. jw devices meet the electrical requirement of each oscillator type. sales and support data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) part no. x /xx xxx pattern package temperature range device device pic16c432 :v dd range 4.0 v to 5.5 v PIC16C432T: v dd range 4.0 v to 5.5 v (tape and reel) temperature range i = -40 ? c to +85 ? c e= -40 ? c to +125 ? c package ss = ssop jw* = windowed cerdip pattern 3-digit pattern code for qtp (blank otherwise). examples: a) pic16c432 -e/p301 = extra temp, pdip pack- age, 4 mhz, normal v dd limits, qtp pattern #301 b) pic16c432 -i/ss industrial temp., ssop pack- age, 4 mhz, industrial v dd limits
pic16c432 ds41140c-page 104 preliminary ? 2000-2013 microchip technology inc.
? 2000-2013 microchip technology inc. preliminary ds41140c-page 105 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2000-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769720 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds41140c-page 106 preliminary ? 2000-2013 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

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